The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs. As this progression has taken place, challenges stemming from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin-like field effect transistor (FinFET) device. A typical FinFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel. Other advantages of FinFET devices include reduced short channel effect and higher current flow.
However, as FinFET devices scale down, a risk of scaling fin width is that this may result in a short channel effect, causing serious mobility degradation. Therefore, to facilitate the scaling of complementary metal-oxide-semiconductor (CMOS) dimensions while maintaining an acceptable performance, there is a need to increase the mobility of carriers in a semiconductor material.